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ABSTRACT
To ensure optimal operating conditions and performance, transistor dimension parameters must be determined accurately. This work investigates the Taguchi approach for device parameter optimization in a 7nm Silicon FinFET, employing design of experiments (DOE) methodologies to improve device performance and efficiency. In this work, the geometric scaling that affect FinFET performance, with an emphasis on the ratio of on-state current (ION) over off-state current (IOFF), threshold voltage (VTH), subthreshold swing (SS) and drain induced barrier lowering (DIBL) are investigated. The Taguchi approach is used to optimize the FinFET model, resulting in improved performance. Furthermore, investigation on the impact of optimized FinFETs on logic circuit performance, notably delay and power characteristics. Moreover, the Silvaco TCAD Simulator is used as the medium of simulation and analysis. The Taguchi method was implemented to determine the most appropriate combination of factors for robust device performance using orthogonal arrays, and signal-to-noise (SN) ratio as the quality characteristic of choices. The factors involved in the design of experiments include the length (LG) and height (HFIN) of the fin as well as the width (WFIN) of the fin at the top region. Using Taguchi’s robust performance signal-to-noise ratio, the combination of parameters was obtained for the ION/IOFF ratio, VTH, DIBL, and SS. The VTH value is 0.7461V for FinFET with LG, WFIN, HFIN being 13 nm, 7 nm, and 35 nm, respectively. The current ratio of 262.072 and SS of 69.4 mV/dec obtained from FinFET when LG is 13 nm, WFIN is 5 nm, and HFIN is 40 nm. For the optimum DIBL, which is 232 mV/V, is gained when the FinFET has LG, WFIN, and HFIN 10 nm, 10 nm, and 35 nm, respectively. The analysis confirms that dimension optimization can significantly enhance FinFET performance. The use of the Taguchi method proved effective in identifying the optimal parameter combinations, and the subsequent application to logic circuits for the development of low-power FinFETs.
