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Description
Digital Signal Processing (DSP) is important in biomedical engineering, enabling thorough analysis of physiological signals. Finite Impulse Response (FIR) filters are preferred in biomedical applications due to their stability and linear phase response. Optimizing adders in FIR filters is crucial to reduce power consumption and enhance efficiency. This project aims to compare the performance of 4-bit Ripple Carry Adder (RCA), 4-bit Carry Save Adder (CSA), and 4-bit Carry Lookahead Adder (CLA) using 180 nm CMOS technology in Cadence Virtuoso software, to obtain a 4-bit adder design with propagation delay less than 50 ps, less than 70 transistors, and a power consumption of below 6 μW. The Mod-GDI technique is applied to optimize performance by reducing the number of transistors in logic gates. Pre-layout simulation results revealed that the 4-bit CLA met all the design objectives, achieving a propagation delay of 13.71 ps, using 52 transistors, and consuming 0.3331μW of power. Post-layout simulations indicated an increase in propagation delay and power consumption due to parasitic effects. Despite these increases, the CLA's performance remained acceptable, confirming its suitability for low-power, high-speed applications in biomedical devices. Specifically, the CLA demonstrated a 25.7% reduction in transistor count, an 18.7% reduction in delay, and a 92.6% reduction in power consumption compared to a reference design.
